The patent the USPTO issued to AUO Corporation on June 23, 2026 — US12667027B2, titled "Routing structure of display screen" — solves a wiring-geometry problem that gets worse as light-emitting panels get larger and their pixel pitch gets finer. Because this is a granted patent rather than a pending application, what follows is a reading of the independent claims as issued: the scope the examiner allowed, not a prediction about what might issue.

The problem the granted claims are directed to is signal timing in a panel driven from a single edge. In the claimed structure, the circuit board and the driver chips sit at a first side of the display screen. One population of light-emitting units — the "first light-emitting units" — is disposed along the two opposite lateral sides that connect to that first side, and a second population — the "second light-emitting units" — sits at the second side opposite the drivers. The wires that carry drive signals therefore have to travel very different physical distances: a short hop to an emitter near the driver edge, a long run up to an emitter at the far side. When wire lengths differ, the RC delay along them differs, and the panel's emitters fire out of step.

The element that does the work is the constraint the claim places on those wire lengths. The independent claim of the first family recites a light-emitting unit routing assembly with a plurality of first routings connected between at least one driver chip and the first (lateral) light-emitting units, a plurality of second routings connected to the second-side units, and a plurality of dummy routings, with the panel providing "3M of routing inlets" at the first side sized to accommodate all three sets. A separate independent claim makes the length-matching quantitative: it caps the difference between any two of the first routings at 2% or less. In plain terms, the patent claims a panel that deliberately equalizes the driver-to-emitter wire lengths across both regions of the screen — and reserves dummy and ground wires to fill the routing channels — so that the timing seen at near and far emitters lines up.

A light-emitting unit routing assembly connected to the driver chips, wherein the light-emitting unit routing assembly comprises: a plurality of first routings connected between at least one of the driver chips and the first light-emitting units, wherein a difference between a total length of one of the first routings and a total length of another one of the first routings is less than or equal to 2%; and a plurality of second routings connected between at least one of the driver chips and the second light-emitting units …— Routing structure of display screen, US12667027B2

How the claimed geometry is built

The granted claims describe the routing in segments rather than as single straight wires. Each first routing is divided into a longitudinal routing segment running in the direction from the first side toward the second side, and a lateral routing segment running across the panel between the two opposite sides; the two segments are joined through a via and can sit on different conductive layers. That two-segment, multi-layer construction is what lets the designer trade longitudinal length against lateral length — one dependent claim recites the case where one routing's lateral length exceeds its longitudinal length while another routing's does the opposite — and still arrive at matched totals. A further independent claim swaps the dummy routings for ground routings tied to a bus wire that surrounds the panel's peripheral area, carrying VSS signals, and ties the geometry to a resolution of M×N with 3M sub-pixel units across the driving edge. The recurring "3M" term reflects the three sub-pixels (red, green, blue) per pixel column that each need an inlet at the driver side.

What distinguishes the issued claim from a generic display interconnect, then, is not that wires run to emitters — every panel has that — but the explicit length-equalization limitation and the inlet-accounting that reserves channels for dummy or ground wires alongside the active first and second routings. Those are the limitations to read against any accused single-edge-driven, multi-driver light-emitting panel.

Where the grant lands in the CPC landscape

The patent sits in the display-device neighborhood of the CPC scheme. Its principal classification is H10W 90/00, the display-technology grouping, placing it among light-emitting display panels and their drive and interconnect structures rather than in a generic printed-circuit or wiring class. That placement is itself informative: the invention is classified as a display structure, consistent with claims that bind the routing geometry to a pixelated M×N panel with per-sub-pixel inlets, a peripheral VSS bus, and driver chips mounted at one edge. For anyone mapping the field, the coordinate to note is the pairing of an interconnect-geometry invention with a display classification — the patent reads on the wiring layer of a panel, but it is filed and examined as panel art.

The grant in context: a same-period AUO display cluster

The routing-structure grant did not issue in isolation. AUO Corporation received two adjacent display grants in the same window, and together they sketch the layers of a light-emitting panel from the diode up to the cover glass. US12666765B2, "Light-emitting element," claims an LED with a first- and second-type semiconductor layer, a light-emitting layer between them, top and bottom electrodes, and a multi-layer film bearing a protrusion portion that extends past the side surface of the semiconductor layer — emitter-level structure, the bottom of the stack. US12666771B2, "Transmissive display device," claims a see-through panel built from a circuit substrate, pixel units of LEDs, first light-shielding structures defining light-transmissive regions that overlap the diodes, a transparent covering layer with holes, a hole-filling portion, and a cover lens — the transmissive micro-LED architecture, the assembled-module level.

Read across the three, the routing-structure patent occupies the interconnect layer between AUO's emitter-level and module-level grants: US12666765B2 claims the individual light-emitting element, US12666771B2 claims a transmissive panel that arrays such emitters behind light-shielding optics, and US12667027B2 claims how the driver chips at one edge are wired to every emitter across the panel with matched timing. Each is a granted patent — examined, allowed, and now enforceable — and the routing structure is the one whose distinguishing limitation is the most legible from the face of the claim: a panel whose driver-to-emitter wires are held to within 2% of one another so that near and far emitters fire in step.